XCR3128XL

Product Summary

XCR3128XL is a 3.3V 128 macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. XCR3128XL A total of eight function blocks provide3,000 usable gates.XCR3128XL Pin-to-pin propagation delays are6.0ns with a maximum system frequency of 145MHz

Parametrics

Symbol Parameter Test Conditions Min. Max. Unit
VOH(2) Output High voltage IOH = 鈥? mA 2.4 - V
VOL Output Low voltage for 3.3V outputs IOL = 8 mA - 0.4 V
IIL Input leakage curret VIN = GND or VCC 鈥? 1010 渭A
IIH I/O High-Z leakage current VIN = GND or VCC 鈥? 1010 渭A
ICCSB Standby current VCC = 3.6V - 100 渭A
ICC Dynamic current(3,4) f = 1 MHz - 1 mA
f = 50 MHz - 30 mA
CIN Input pin capacitance(5) f = 1MHz - 8 pF
CCLK Clock input capacitance(5) f = 1MHz - 12 pF
CI/O I/O pin capacitance(5) f = 1 MHz - 10 pF

Features

(1)Lowest power 128 macrocell CPLD;
(2)6.0 ns pin-to-pin logic delays;
(3)System frequencies up to 145MHz;
(4)128 macrocells with 3,000 usable gates;
(5)Available in small footprint packages;
-144-pin TQFP (108 user I/O pins);
-144-ball CS BGA (108 user I/O);
-100-pin VQFP (84 user I/O);
(6)Optimized for 3.3V systems;
-Ultra low power operation;
-5V tolerant I/O pins with 3.3V core supply;
-Advanced 0.35 micron five layer metal EEPROM process;
-Fast Zero Power? (FZP) CMOS design technology;
(7)Advanced system features;
-In-system programming;
-Input registers ;
-Predictable timing model;
-Up to 23 available clocks per function block ;
-Excellent pin retention during design changes;
-Full IEEE Standard 1149.1 boundary-scan (JTAG);
-Four global clocks ;
-Eight product term control terms per function block;
(8)Fast ISP programming times;
(9)Port Enable pin for additional I/O;
(10)2.7V to 3.6V supply voltage at industrial temperature range; (11)Programmable slew rate control per output;
(12)Security bit prevents unauthorized access ;
(13)Refer to XPLA3 family data sheet (DS012) for architecture description