HY57V561620

Product Summary

HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.
HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
HY57V561620 Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive
read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)

Parametrics

Part No. Clock Frequency Power Organization Interface Package
HY57V561620T-HP 133MHz Normal 4Banks x 4Mbitsx16 LVTTL 400mil 54pin TSOP II
HY57V561620T-H 133MHz
HY57V561620T-8 125MHz
HY57V561620T-P 100MHz
HY57V561620T-S 100MHz
HY57V561620LT-HP 133MHz Lower
Power
HY57V561620LT-H 133MHz
HY57V561620LT-8 125MHz
HY57V561620LT-P 100MHz
HY57V561620LT-S 100MHz

Features

(1)Single 3.3V 卤 0.3V power supply;
(2)All device pins are compatible with LVTTL interface;
(3)JEDEC standard 400mil 54pin TSOP-II with 0.8mm ;
(4)of pin pitch;
(5)All inputs and outputs referenced to positive edge of ;
(6)system clock;
(7)Data mask function by UDQM and LDQM;
(8)Internal four banks operation;
(9)Auto refresh and self refresh;
(10)8192 refresh cycles / 64ms ;
(11) Programmable Burst Length and Burst Type;
(12) - 1, 2, 4, 8 and Full Page for Sequential Burs;
(13) - 1, 2, 4 and 8 for Interleave Burst;
(14)Programmable CAS Latency ; 2, 3 Clocks

Diagrams

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