(Hong Kong)
Product Summary
The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V.
The CY7C1339B supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC.
The CY7C1339B All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.Maximum access delay from the clock rise is 3.5 ns (166-MHzdevice).
The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.
Parametrics
7C1339B-166 7C1339B-133 7C1339B-100 Unit
Maximum Access Time 3.5 4.0 5.5 ns
Maximum Operating Current 420 375 325 mA
Maximum CMOS Standby Current 10 10 10 mA
Features
(1)Supports 100-MHz bus for Pentium? and PowerPC;
operations with zero wait states;
(2)Fully registered inputs and outputs for pipelined ;
operation;
(3)128K 脳 32 common I/O architecture ;
(4)3.3V core power supply; (7)2.5V / 3.3V I/O operation;
(5)Fast clock-to-output times ;
鈥?.5 ns (for 166-MHz device);
鈥?.0 ns (for 133-MHz device);
鈥?.5 ns (for 100-MHz device);
(6)User-selectable burst counter supporting Intel;
Pentium interleaved or linear burst sequences;
(7)Separate processor and controller address strobes;
(8)Synchronous self-timed writes;
(9)Asynchronous output enable;
(10)Offered in JEDEC-standard 100-pin TQFP and 119-ball ;
BGA packages;
(11)鈥淶Z鈥?Sleep Mode and Stop Clock options
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