XC3S1200E-4FTG256C

Product Summary

The Spartan-3E Field-Programmable Gate Array (FPGA) XC3S1200E-4FTG256C is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The device offers densities ranging from 100,000 to 1.6 million system gates. The XC3S1200E-4FTG256C builds on the success of the earlier Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. The XC3S1200E-4FTG256C, combined with advanced 90 nm process technology, delivers more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Parametrics

XC3S1200E-4FTG256C absolute maximum ratings: (1)Internal supply voltage:–0.5V to 1.32V; (2)Auxiliary supply voltage:–0.5V to 3.00V; (3)Output driver supply voltage:–0.5V to 3.75V; (4)Input reference voltage:–0.5V to VCCO+0.5V; (5)Voltage applied to all User I/O pins and Dual-Purpose pins:–0.5V to VCCO+0.5V; (6)Voltage applied to all Dedicated pins:–0.5V to VCCAUX+0.5V; (7)Electrostatic Discharge Voltage:Human body model:–2000V to +2000 V, Charged device model:–500V to +500V, Machine model:–200V to +200V; (8)Junction temperature:- 125℃; (9)Storage temperature:–65℃ to 150℃.

Features

XC3S1200E-4FTG256C features: (1)Very low cost, high-performance logic solution for high-volume, consumer-oriented applications; (2)Proven advanced 90-nanometer process technology; (3)Multi-voltage, multi-standard SelectIO interface pins; (4)True LVDS, RSDS, mini-LVDS differential I/O; (5)3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling; (6)Enhanced Double Data Rate (DDR) support; (7)Densities up to 33,192 logic cells, including optional shift register or distributed RAM support; (8)Efficient wide multiplexers, wide logic; (9)Fast look-ahead carry logic; (10)Enhanced 18 x 18 multipliers with optional pipeline; (11)IEEE 1149.1/1532 JTAG programming/debug port; (12)Up to 648 Kbits of fast block RAM ; (13)Up to 231 Kbits of efficient distributed RAM; (14)Clock skew elimination (delay locked loop); (15)Frequency synthesis, multiplication, division; (16)High-resolution phase shifting; (17)Wide frequency range (5 MHz to over 300 MHz); (18)Low-cost, space-saving SPI serial Flash PROM; (19)x8 or x8/x16 parallel NOR Flash PROM; (20)Low-cost Xilinx Platform Flash with JTAG; (21)MicroBlaze, PicoBlaze embedded processor cores; (22)Fully compliant 32-/64-bit 33/66 MHz PCI support ; (23)Low-cost QFP and BGA packaging options.

Diagrams